0
lw
3
destination
register
r1
source
register
r0
source
immediate
28
0
4
lw
3
destination
register
r3
source
register
r0
source
immediate
32
1
8
add
3
destination
register
r2
source
register
r0
source
register
r0
2
12
beq
3
source
register
r2
source
register
r3
source
immediate
3
3
16
add
3
destination
register
r2
source
register
r2
source
register
r1
4
20
j
1
source
immediate
3
5
24
nop
0
28
3
destination
register
r0
source
register
r0
source
register
r0
7
32
8